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There is great interest in “digital twins” to improve many aspects of semiconductor manufacturing, from increased device yield and performance, reduced consumption of energy and materials, increased flexibility, and to enable rapid uptake and scaling of new material, equipment, and process innovations. The digital twin has both physical and virtual components, with bilateral communication and control; the hope is to enable a wide range of models (of equipment, processes, wafers) at different fidelities (physical to simplified empirical, and machine-learning enabled), to support a wide range of “smart” functionalities. The road to digital twins goes through and builds upon many well-trodden paths. Here, several lines of research at MTL since the late 1980’s are highlighted, beginning with elements of the MIT Computer Aided Fabrication Environment including process flow languages, to DOE/Opt methods for automated surrogate model construction, and run by run control to track and compensate for equipment state and wear in CMP and other unit processes. The development of “statistical metrology” methods encompassed characterization and modeling of semiconductor variation, with layout pattern dependent models to identify “hot spots” in planarization, dishing, and erosion for a given design, as well as to guide dummy fill generation. An evolution from statistical to ML/AI approaches, particularly Bayesian methods, enabled design for manufacturability (DFM) for rapid MOSFET characterization, and then rapid fabrication process tuning, as well as AI-enabled anomaly detection. These and other paths bring us to an exciting next stage of the journey: by harnessing advances in sensing and data collection, AI methods, and computational power not possible at the beginning, the community is poised to create and deploy digital twins for semiconductor manufacturing.