Principal Investigator Duane Boning
Semi-additive electro-chemical plating (ECP) is a common process for fabricating copper interconnects in many advanced packaging technologies, such as Wafer Level Integrated Fan Out (InFO) packaging. While cost efficient, this process suffers from thickness variations in the height of the plated copper. The most significant of these variations are layout dependent, where areas with dense interconnects plate slower than sparse areas. If left unchecked, these variations can lead to significant complications in later stages of the fabrication process, and ultimately to decreased electrical performance of the final packaged device. Previously, there were limited methods for predicting these variations, and foundries had to rely on experimentally determining which layouts would perform acceptably. Recently, we have developed a model that predicts these variations and allows errors to be predicted and corrected without the need to first fabricate the layout in question.
While a model based on fundamental physics could in principle be developed to predict these variations, we instead develop an empirical model based on experimental data. This approach is well suited for many industrial applications, as empirical models can often be developed more quickly, without a significant loss of accuracy, and can be rapidly tuned or adapted to accommodate effects whose causes are uncertain. The ECP model is divided into four stages as summarized in Figure 2. First, the effective pattern density of each point on the layout is determined with a learned spatial filter. These pattern densities are then mapped to effective conductances using a ratio-of-polynomials approximation. Next, these conductances are masked with the original layout, as photoresist prevents copper from growing in unwanted areas. Finally, the current flowing through each point of the wafer is solved for, and these currents are then converted to the plating height at each point in the layout.