Principal Investigator Tomas Palacios
As continued scaling of silicon field-effect transistors (FETs) grows increasingly challenging, alternative paths for improving digital system energy efficiency are actively being pursued. These paths include replacing the transistor channel with emerging nanomaterials (such as carbon nanotubes: CNTs), as well as utilizing negative capacitance effects in ferroelectric materials in FETgatestacks, e.g., to improve sub-threshold slope beyond the 60 mV/decade limit (at temperature = 300 degrees K) for conventional FETs (which in itself is difficult to achieve due to short-channel effects). However, which path provides the largest energy efficiency benefits, and whether these multiple paths can be combined to achieve additional energy efficiency benefits, is still unclear.
Here, we experimentally demonstrate the first negative capacitance carbon nanotube FETs (CNFETs: combining the benefits of both carbon nanotube channels (which offer superior electrostatic control vs. silicon-based FETs, simultaneously with superior carrier transport) and negative capacitance effects. We experimentally demonstrate negative capacitance CNFETs (NC-CNFETs) that achieve sub-60 mV/decade sub-threshold slope. Across 50 NC-CNFETs, our experimental results show an average sub- threshold slope of 55 mV/decade at room temperature, compared to 70 mV/decade for baseline CNFETs, i.e., without negative capacitance. The average on-state drive current (ION) of these NC-CNFETs improves by 2.1× vs. baseline CNFETs, for the same off- state leakage current (IOFF). This work demonstrates a promising path forward for future generations of energy-efficient electronic systems.