Entry Date:
January 24, 2019

Dielectric Breakdown in a Novel GaN Power Field-effect Transistor

Principal Investigator Jesus del Alamo


Gallium Nitride (GaN) transistors are increasing in popularity for high voltage power electronics applications. The most promising device structure is the
metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). MIS-HEMTs are of interest because of their high breakdown voltage, low gate leakage current, and high channel conductivity. However, before commercial deployment, more work is required to improve the reliability and to reduce the instability of GaN MIS-HEMTs. Work is focused on the characterization, ON-state time-dependent dielectric breakdown (TDDB), OFF-state TDDB, and Weibull sta- tistical analysis of a novel GaN transistor. Our goal is to study and understand the physics behind gate dielec- tric breakdown in this device in order to assess device robustness to prolonged operation. We have complet- ed many studies on these devices to determine break- down location along the channel, chip to chip variation, temperature dependence, voltage dependence, thresh- old voltage shift, and projected lifetime.

During sustained ON-state bias at a high voltage, these devices exhibit trapping effects, stress-induced leakage current (SILC), progressive breakdown and eventually, hard dielectric breakdown. This is comparable to past MIS-HEMT studies in our group. As expected, hard breakdown time decreases as both temperature and drain voltage (VDS) are increased.

OFF-state TDDB proved difficult because of parasitics, test implementation, and a high variability of over three orders of magnitude in hard breakdown time. An alternative methodology was used, increasing VDS in a linear ramp until hard breakdown occurred. This allows us to characterize the instantaneous breakdown voltage of the devices. Analyzing these results using a Weibull distribution shows a two- slope distribution. This can mean that two breakdown mechanisms are present or that there are multiple layers in the gate stack with different rates of defect generation.

Present research focuses on determining a methodology to accurately evaluate device lifetime during the application of a large drain bias while the device is in the OFF state.