Principal Investigator Duane Boning
Silicon photonics has garnered a large amount of interest in recent years due to its potential for high data transfer rates and for other, more novel applications. One attractive feature of silicon photonics is its relatively seamless integration with existing CMOS fabrication technologies. That means, however, that it is subject to similar random and systematic variations as are known to exist in CMOS manufacturing processes.
One common source of process variation is Line Edge Roughness (LER), which occurs during lithography. Since LER produces random perturbations to the component geometry, it is likely to influence the light- guiding abilities of photonic components and devices subject to LER.
We study the effect of LER on the performance of a fundamental component, the Y-branch, through virtual fabrication simulations. Ideally, the Y-branch transmits the input power equal to its two output ports. However, imbalanced transmission between the two output ports is observed when LER is imposed on the Y-branch depending on the statistical nature (amplitude and correlation length) of the LER. The imbalance can be as low as 1% for small LER amplitudes, and reach up to 15% for large LER amplitudes. These results can be captured as worst-case corner models and included in variation-aware photonic compact models.