Design of Ultra-Low Power Variation Aware, Time-Interleaved A/D Converters

This project is focused on the development of the design of high-performance and low-power analog to digital converters (ADC) using a time-interleaved (TIADC) design for a successive-approximate-register (SAR) architecture.

The project tackles the problem of low-energy integrated circuit design from the viewpoint of process variations, and as a result, it adds a new and needed perspective on IC energy management and sustainability.