Entry Date:
February 11, 2014

CAD Methodologies in Tools for Variations-Aware Minimum Energy Design of Nanoelectronic Circuits and Systems


This research is motivated by the observed trends in semiconductor technology and design.

One difficult trend is the steady increase in process variability with the scaling of feature sizes in semiconductor components. Such an increase expresses itself in significant uncertainties on various device and circuit metrics such as performance, power-consumption, and reliability.

Another such trend is the continued increase in observed power-demand densities in high-performance digital chips such as microprocessors and digital-signal processing chips. One increasingly important contributor to power demand is the leakage power of the chip, which is the power consumed when the chip is idle. This leakage power is very sensitive to variations in device characteristics and environmental variables, especially temperature.

When these trends are put together in the context of designing energy-efficient multi-core, multi-threaded processors with billions of devices, the need for CAD tools capable of addressing semiconductor variability particularly in a low-power design methodology becomes clear.

This research is directly relevant to Masdar Institute’s mission from a variety of angles, including:

(*) It tackles the problem of low-energy integrated circuit design from the viewpoint of process variations, and as a result, it adds a new and needed perspective on IC energy management and sustainability.
(*) It is interdisciplinary, and can draw on the strengths of the Masdar Institute faculty in the areas of micro-electronic fabrication, device engineering, circuit design, and CAD.