Integrated Optical Logic

Future optical networks require the number of optical-to-electrical-to-optical conversions to be minimized. To allow the optical data to remain in the optical domain, the optical core requires some logic functionality. Therefore, the aim of this project is to model and to produce a modular monolithically-integrated all-optical unit cell capable of performing a complete set of Boolean operations at speeds of 100s of gigabits per second. Optical logic operations, wavelength conversion, and other advanced optical switching schemes can be implemented using the design. The basic structure consists of a balanced Mach-Zehnder interferometer with an InGaAsP-based semiconductor optical amplifier in each arm. By investigating the device design and fabrication tolerances using the beam propagation method and finite-difference time-domain techniques, the critical device dimensions were modeled prior to fabrication.

A set of design and simulation tools is used to develop the design rules, to identify tradeoffs, to determine fabrication tolerances, and to estimate the effects of imperfections in semiconductor processing on the device’s performance. The beam propagation method (BPM) simulations are used to model passive waveguides, multimode interference couplers, and asymmetric twin-waveguide structures with adiabatic tapers. Three-dimensional, finite-difference, time-domain (FDTD) calculations were used to estimate the reflections between the various components by considering a small computational domain around each abrupt interface. The FDTD computations confirm that the reflectivity of the adiabatic tapers with blunt tips is well below 0.0001. Custom MATLAB scripts are used to assess the tradeoffs in the SOA performance for both linear and non-linear applications in photonic integrated circuits. One of the goals of this work is to produce design rules that specifically address the design of the SOAs for switching applications. The phase in the SOAs is modeled in order to study cross-phase modulation in a balanced MZI with an SOA in each arm.

The creation of the optical unit cell requires multiple components such as SOAs and multi-mode interference couplers to be integrated together via low-loss passive waveguides. The passive waveguide consists of three layers of In0.8Ga0.2As 0.45P0.55 separated by InP. The SOA consists of a 200 nm thick layer of In0.56Ga0.44 As0.94P0.06 with 100 nm thick In0.8Ga0.2As 0.45P0.55 cladding layers. The asymmetric twin waveguide approach is employed for the monolithic integration of active devices with passive components in which the active devices are stacked vertically on a lower passive waveguide. The use of an adiabatic taper coupler allows the optical signal to move from the passive waveguide to the active waveguide.

Prototypes of the all-optical logic unit cell have been fabricated using the facilities within the Microsystems Technology Laboratory (MTL), the Nanostructures Laboratory (NSL) and MIT Lincoln Laboratory. The current generation design combines both the active and passive devices into single die suitable for a step-and-repeat mask set, allowing for sharper tapers and smoother waveguide bends. Processing improvements include depositing the base metal for the top-side contact prior to any III-V etching, minimizing the amount of InP-based etching through the use of trenches, and using dedicated III-V ICP RIE etcher at Lincoln Laboratory. Complete optical logic structures have been fabricated.

The fabricated devices are currently being characterized both at M.I.T. and at M.I.T. Lincoln Laboratory. The passive waveguides have a measured loss of 0.89dB/cm. In addition, diode characteristics have been measured for the SOAs. An effort to improve upon the fabricated devices in order to lower the contact resistance and to improve the planarization uniformity across the chip is underway. A new contact metal mask has been designed to improve the current injection and to allow for easier probing of the SOAs.