Near-Room-Temperature Processed Metal Oxide Field Effect Transistors for Large-Area Electronics

Recently, sputtered metal-oxide-based field effect transistors (FETs) have been demonstrated with higher charge carrier mobilities, higher current densities, and faster response performance than amorphous silicon FETs, which are the dominant technology used in display backplanes. Furthermore, the optically transparent semiconducting oxide films can be deposited in a near-room-temperature process, making the materials compatible with future generations of large-area electronics technologies that require use of flexible substrates. It is possible to process FETs by shadow-mask patterning, but this method limits the range of feature sizes, accuracy of pattern alignment, and scalability of the process to large substrates. Consequently, the project aims to develop a low-temperature, lithographic process for metal oxide-based FETs, similar to one developed for organic FETs, that can be integrated into large-area electronic circuits.

Using an organic polymer, parylene, as the gate dielectric and indium-tin-oxide (ITO) for source/drain contacts, top-gate, lithographically processed FETs have been fabricated on glass substrates using ZnO:In2O3 channel layers.

A reproducible FET process requires consistent control of mate¬rial properties of the metal oxide semiconductor film. We examine the effect of varying deposition conditions (e.g., target composition, O2 partial pressure, film thickness) and post-deposition treatment on DC- and RF-sputtered amorphous oxide thin films in the In2O3-ZnO system. The electrical properties of thin films are determined through resistivity and Hall measurements. These measurements are used as a guide to determine processing conditions for the fabrication of oxide-based field effect transistors and circuits.