Field Emitter Array Flat Panel Displays for Head-Mounted Applications

Advances in nanostructure technology have made feasible small, high-resolution, high-brightness and high-luminous-efficiency field-emitter-array sources for Head-Mounted Displays (HMDs). HMDs are expected to have a variety of applications in military, medical, commercial and entertainment fields. The technology most commonly used in deployed HMD systems is the CRT which is bulky, because of the use of a single electron gun to generate images on a cathodoluminescent screen, but has the most desirable attributes of high luminous efficiency, high brightness and easy image rendition. However, the relay optics required for see-through HMDs become complicated because of the bulky nature of the CRT. For other applications, such as entertainment virtual reality, the most commonly used image source is the backlit Active- Matrix-Liquid-Crystal Display (AMLCD), which is thin and has high resolution. Furthermore, the addressing electronics are integrated on the same substrate as the image source. However, the backlit AMLCD image source does not have sufficient brightness nor luminous efficiency to make it suitable for application to see-through HMDs.

This approach to demonstrating a small, high-resolution, high-luminous-efficiency and highbrightness display is the field-emitter-array Flat-Panel Display (FED) which incorporates a highdensity, high-performance array of low-voltage field emitters. CMOScontrolled electron emission from the tips impinges on a cathodoluminescent screen. It is thus possible to integrate the addressing and signal conditioning electronics on the same substrate as the Field Emitter Arrays (FEAs). The main advantage of this approach is the reduction of the number of wires and bond pads from about 2,000 to about 50. For example, it will be difficult to attach > 2,000 wires to bond pads in an area of 1.5" x 1.5" and obtain ultra-high vacuum in the display envelope. High resolution (>1000 dpi) FEDs are only possible if the addressing/driver and other signal conditioning electronics are integrated on the same substrate as the field emitter arrays.

The initial objective is to demonstrate low-voltage field-emitter arrays fabricated using interferometric lithography for future integration with Si CMOS technology. Interferometric lithography is used to define the emitter cone arrays that are spaced 200 nm tip-to-tip and have <50 nm gate-to-emitter separation. Fabricated cone-field-emitter arrays with a 320-nm period have demonstrated emission currents of 1 mA at a gate voltage of 20V from 900 cones in a 10 É m x 10 É m area. This current is more than adequate for a brightness of 1000 fL at a screen voltage of 500V.

Initial efforts focused on modeling the scaling behavior of FEA devices. Numerical simulation and computer models to predict FEA performance have been developed and continue to be refined. These models allow us to explore the effects of device scaling on the emitter’s output characteristics. The results of this study have directed our fabrication efforts toward devices whose performance will not only be better, but more dependent on geometries that can be well controlled in the manufacturing process. Simulation results indicate that we will be able to increase the current density and reduce the operating voltage, by decreasing the tip-to-tip separation to 200 nm.

FEAs of 200 nm period have been fabricated by using interferometric lithography and standard processing techniques. Additional metallization layers and conventional lithography were used to create discrete Molybdenum Spindt arrays for electrical characterization. Standard CMOS processing techniques have been also been combined with the interferometric lithography to form 200 nmperiod arrays of Si etched cones. TEM analysis of the oxidation sharpened emitter tips showed tips with radii as small as 2.5 nm.

A semi-automated Ultra High Vacuum (UHV) probe chamber has been developed for the electrical characterization of FEAs. This test bed allows the performance of the arrays to be evaluated without the lengthy overhead of vacuum packaging devices. Device performance has been shown to be not only dependent on the device physical structure, but also on surface contamination that may have resulted during fabrication and MEMS processing. The UHV probe chamber has the capability to do device conditioning including plasma surface cleans and wafer bake-out. The system is combine with a UHV Scanning Maxwell Microscope, and allows the future expansion to include other surface analysis chambers including a Kelvin Probe and Auger.

Electrical characterization of the 100 nm-aperture Molybdenum arrays and silicon arrays, (both 200 nm tip-to-tip spacing), has shown that arrays can operate at voltages as low as 16 volts and 13 volts respectively. We have demonstrated initial testing of low-gate-voltage FEAs with discrete solid state devices. We replace the resistor that previous approaches have used to limit and control emission current with a MOSFET. Current control is critical to the uniformity of brightness across the display. It was possible to control the emitted current density and increase temporal stability using the gate voltage of the transistor load. This may enable analog voltage gray scale or temporal gray scale.