Data-Dependent Successive-Approximation-Register Analog-to-Digital Converter

This work on successive-approximation-register (SAR) analog-to-digital converters (ADCs) (Figure 1) aims at improving data-dependent savings in energy in key components of a SAR ADC by leveraging the information available from the signal’s immediate past samples and the signal type. The dominant energy consuming components are the DAC and comparator.

Energy expenditure in DAC per sample conversion depends on the DAC topology and sequence of steps taken during successive approximations. Energy in a comparator is directly proportional to the number of comparisons done per sample conversion. A design with data-dependent savings takes advantage of the correlation between successive samples in completing the conversion in fewer bit-cycles and also operate DAC energy-efficiently.

Previous work presents data-dependent savings by doing least-significant-bit (LSB) first successive approximation to convert an input sample. By starting with a previous sample and doing LSB-first, the algorithm converges in a fewer number of cycles than conventional most-significant-bit (MSB) first SAR conversion. Fewer cycles translate into energy savings in the comparator and DAC. Another work developed successive approximation algorithms to find a sub-range from the full range in a few cycles before carrying on a binary search in this small range. In this work, we investigate a SAR ADC with a search algorithm based on the statistical characteristics of the signal for optimum energy expenditure.