Negative Capacitance Field Effect Transistors (NCFETs) have emerged as promising candidates for CMOS technology scaling due to their potential for sub-60-mV/decade operation by utilizing negative capacitance effects in ferroelectric materials. A ferroelectric oxide (FE-oxide) capacitor in series with the normal gate-stack capacitor of a conventional MOSFET forms the NCFET. A physics-based compact model, MVSNC, is proposed to capture the device–behavior under static and dynamic operating conditions using the MVS-framework for the underlying MOSFET and the Landau-Khalatnikov (L-K) equation to model the FE-oxide.
The baseline MOSFET is characterized against Intel- 45nm data and while PZT oxide of tFE=5 nm is chosen for NCFETs. The model is implemented in Verilog-A, and transient simulations are performed using a commercial simulator (ADS®). The simulated device-level IV- and CV-characteristics of NCFET and baseline FET are shown. With same off-currents, NCFETs exhibit steep subthreshold-swing (SS) due to stabilization of negative capacitance (NC)-state in FE-oxide and VG,int-amplification compared to VG. Higher on-current (at same VG) with reduced or negative DIBL at certain VD regimes can also be seen. The CV-characteristics show capacitance-amplification in sub-threshold regime.
Leakage in FE-oxide that can potentially remove the SS-steepness advantage in NCFETs is studied along with work-function engineering (WFE) that is proposed to mitigate the impact of FE-leakage. By shifting the FE-oxide’s Q-V curves along voltage-axis, WFE allows NC-state to be reached at low-VDD. The energy-delay (E-td) figure-of-merit of the NCFETs can be compared against baseline CMOS using loaded ring-oscillator (RO)-simulations. 21-stage ROs loaded with a constant capacitance CL whose value is equal to total on-capacitance (CGG at VD=0 and VG=1V) of the constituent baseline FETs of inverter are shown. Here, VDD is swept to get the energy-delay plot. The figure shows reduced E-td in NCFETs even under leakage because of lower switching loss in CL (0.5CLV2DDf). The benefit of lower E-td with NCFETs is significant at scaled VDD nodes and can be preserved even under DE-leakage scenarios by adopting WFE.