Principal Investigator Ruonan Han
Parametric frequency conversion using nonlinear reactive devices (e.g. MOS varactor) is important for passive high-frequency signal generation. In general, we need to find the optimum conditions of the device device, prevent harmonic leakage, and minimize the circuit structure complexity (and loss). To achieve higher energy efficiency and bandwidth, we designed a very compact partially-coupled ring structure that utilizes the mode orthogonality of different harmonic waves.
Chip prototype (RFIC 2012, T-MTT 2013): 480-GHz passive frequency doubler in 65-nm CMOS. It has a measured conversion loss of 14.3 dB and an unsaturated output power of 230 μW. This doubler provides the highest output frequency among all CMOS multipliers.