Hardware Efficient Algorithms and Circuit Architectures for Wireless Sensor Applications

In most wireless sensor applications ranging from environmental monitoring to medical implants, the utility of the wireless sensor node is limited by its finite energy source and the replacement cost of the node once the source has been exhausted. In this work, we examine this problem from the perspective of the sensor node's energy consumption and explore algorithms and circuit architectures that could significantly improve on the energy-efficiency of wireless sensor nodes and hence extend their lifetime and utility. We show the typical circuit blocks used in sensors for medical monitoring and their associated energy cost and power consumption at a given sample rate. The radio power is typically dominant so any reduction in the amount of data transmitted essentially reduces the system power likewise. In applications such as implantable neural recording arrays, the high energy cost to transmit a bit of information and the radio’s limited bandwidth actually necessitate data compression or filtering at the sensor in order to reduce energy consumption and data throughput.

In this work, we present the design and implementation of a new sensor system architecture based on the theory of compressed sensing that more efficiently reduces the number of bits transmitted while perserving the original signal information. As results from our first work show, this approach reduces the average radio power by exploiting signal sparseness to encode the data at a high compression factor. The reconstruction process also enables power reduction in the frontend circuitry by relaxing the noise and resolution requirements of the AFE and ADC. Unlike event detection based data compression, this approach enables a faithful reconstruction of the entire original signal and is applicable across a variety of signals without knowing the signal details a priori. While most of the results and examples presented are in the context of medical applications, they can be generally applied to other fields as well. In conjunction with the compressed sensing work, a new DAC switching algorithm for SAR ADCs aimed at reducing area and enabling more parallel architectures has also been developed.