Principal Investigator Anantha Chandrakasan
Project Website http://www.ifc.gatech.edu/
On-chip interconnect has become a dominant factor in determing the performance and power dissipation of digital integrated circuits. In FPGAs, more than 80% of the power is attributed to on-chip interconnects. Clock skew and jitter have placed bounds on clock rates that can be achieved in microprocessors. Parasitic interconnects prevent integrating large digital systems with sensitive analog circuits. We are exploring "optical PLLs" architectures to distribute 10GHz clocks, use of 3-D technologies to allow mixed-signal integration, tools and methodologies for substrate coupling, and interconnect driven architectures.
The goal of the proposed research is to discover new solutions that will enable the semiconductor industry to transcend interconnect limitations.