Chemical Mechanical Polishing (CMP)

The ever-increasing demand for high-performance microelectronic devices has motivated the semiconductor industry to design and manufacture Ultra-Large-Scale Integrated (ULSI) circuits with smaller feature size, higher resolution, denser packing, and multi-layer interconnects. The ULSI technology places stringent demands on global planarity of the Interlevel Dielectric (ILD) layers. Compared with other planarization techniques, the Chemical Mechanical Polishing (CMP) process produces excellent local and global planarization at low cost. It is thus widely adopted for planarizing inter-level dielectric (silicon dioxide) layers. Moreover, CMP is a critical process for fabricating the Cu damascene patterns, low-k dielectrics, and shallow isolated trenches. The wide range of materials to be polished concurrently or sequentially, however, increases the complexity of CMP and necessitates an understanding of the process fundamentals for optimal process design.