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ILP Institute Insider

October 5, 2015
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3D Chips Mix and Match Integrated Circuit Layers

We demand cell phones and computers become ever smarter, thinner, lighter, less-power hungry, and cheaper. In one dramatic example, to exploit the opportunities of ultra-high-speed 5G mobile networks, future mobile phones “will need to have a lot more complexity in a specific volume,” says Rabindra Das, technical staff member at MIT Lincoln Laboratory.

Traditionally, engineers have added complexity and performance to chips by scaling down feature size in integrated circuits (ICs). Today, as silicon scaling approaches economic limits, that’s not so easy.

Fortunately, says Das, “we have a three-dimensional chip technology that can solve some of these technical challenges.”

Mobile phones are just one set of promising applications for the Lincoln Lab 3D integrated circuit technology, which can create highly dense chips that can also incorporate multiple heterogeneous IC layers with various technologies and materials. The ability to tightly connect heterogeneous IC layers allows designers creating 3D chip structures to optimize each layer, potentially both improving performance and lowering costs, emphasizes Donna-Ruth Yost, an associate staff member at Lincoln Lab.

One example of such integration may aid in integrating CPUs with their short-term memory cache. One common 3D method to tighten the connection is to bump-bond the cache on top of the microprocessor. The Lincoln Lab layered integration approach, however, offers major advantages over classic bump-bonding.

“We are not just stacking two chips, we are stacking just the active layers, with really short interconnects,” explains technical staff member Chenson Chen. Such designs can boost circuit speed, decrease power losses, and allow highly dense connections.

Other examples of applications that highlight the advantages of heterogeneous IC layers come from megapixel focal-plane imagers, in which the imager’s photosensitive layer can be completely dedicated to an array of pixels, with readout electronics stacked behind it.
Lincoln Laboratory’s wafer-scale 3D integrated circuit technology can create extremely dense 3D chips, as shown in this cross-section of a chip with three CMOS tiers. Importantly, the technology also can integrate layers incorporating different technologies and materials.
In one successful early prototype imager, Chen notes, a laser-radar chip was constructed by combining a single-photon-sensitive avalanche photodiode layer with analog control circuitry in a second tier and a high-speed digital counter in a third tier.
These 3D integrated circuits are shown to the same scale. The Lincoln Lab through-oxide via technology, shown on the right, has achieved much denser configurations than bump-bonding and thru-silicon via interconnects.
Another more recent prototype is a short-wave infrared imager that combines an indium gallium arsenide photodiode layer with silicon CMOS readout circuitry, and packs in pixels more tightly than in previously reported devices.
In assembling three tiers of wafers into a 3D chip, each wafer is flipped and bonded, its handle silicon layer is removed, and openings for the via interconnects are filled with tungsten.
Other potential applications arise for combining photonics with silicon ICs to handle chip input/output tasks. Using photonics components for I/O can increase throughput and cut power consumption. These are very important benefits for server farms and cloud storage, but such integration raises many barriers.

The Lincoln Lab team has successfully demonstrated a prototype design that bonds a CMOS layer to a photonics layer with silicon waveguides and germanium detectors In a parallel effort, they also realized an on-chip 980-nm external-cavity laser by flip-chip aligning and bonding a semiconductor optical amplifier to a wafer containing silicon-nitride waveguides in which a distributed Bragg reflector (DBR) grating structure had been fabricated. These technologies can be combined to demonstrate integrated electronic-photonic circuits.

Building 3D Bonds
One recent approach to 3D integration uses thru-silicon “via” (TSV) plug interconnects etched through a silicon wafer. This technique utilizes thicker wafers and the density of the interconnect is limited by the wafer thickness and aspect ratio (depth to diameter ratio) of the TSVs.

In contrast, the Lincoln Lab method integrates only the circuit layers themselves, removing the silicon substrates leaving the active circuitry in the silicon-on-insulator (SOI) wafers. Each additional circuit layer adds only 10 microns of oxide thickness and circuitry rather than 100-700 microns of silicon substrate. For a three-tier chip, the top two wafers must be SOI in which the active silicon layer is separated from a silicon substrate “handle” by an insulating buried oxide.

The vias through oxide can be short, compact, and highly dense. (In 2009 the team achieved the densest 3D interconnection between a short wave infrared imager and a CMOS read out wafer that had been demonstrated at that time.)
The Lincoln Lab 3D integration approach promises significant benefits for combining electronics with photonics. One prototype design successfully bonds a CMOS wafer to a wafer with silicon waveguides and germanium detectors, adding slab-coupled optical waveguide lasers (originally invented at Lincoln Lab) by a separate die-to-wafer process.
In assembly, the second-tier wafer is flipped and its circuit layer is aligned and bonded to the first-tier wafer, then ground and etched to remove its silicon handle layer and expose its buried oxide. Concentric 3D via openings are etched through the buried oxide, and then filled with tungsten plugs that form the interconnects. The third-tier layer can be added in the same way, and then etched on top to receive back-metal connections.

Lincoln Lab developed three key enabling technologies for this process, says research associate Keith Warner. First is the highly precise alignment and bonding between wafers, using infrared cameras and achieving 0.25 micron wafer-to-wafer alignments. Second is the low-temperature oxide-oxide wafer bonding that does not require epoxy. Third is the set of concentric 3D vias that electrically connect the layers.

The process works with existing integrated circuit fabrication techniques and with wafers from any foundry that meet specified criteria, Warner emphasizes.

Adding Dimensions to 3D Chip Use
While pushing the technology forward, Lincoln Lab has also made it widely available to academic groups. “We’ve enabled the next generation of engineers to start thinking in 3D,” says Yost.

The Defense Advanced Research Projects Agency (DARPA), which has funded the development of the integrated technology, has made it available to more than 40 circuit-design research groups. More than 100 3D designs have been fabricated, including stacked memories, field programmable gate arrays, and mixed signal and radiofrequency circuits, she says.

One area of particular future interest is the world of highly power-efficient computing, ranging from handheld devices to drones and Internet of Things devices. In these applications, the 3D integration’s potential for massively parallel vertical interconnects may aid in performance, Chen says.

Overall, the Lincoln Lab approach offers “multiple building blocks for 3D technologies, and we’re not limited to just three building blocks in a chip,” Das sums up.

The Lincoln Lab technology is covered by a number of patents on various techniques. Businesses interested in learning more about MIT integrated circuit technologies should contact the Technology Licensing Office at tlo@mit.edu, 617-253-6966 or web.mit.edu/tlo.

Research News

October 5, 2015

Big range of behaviors for tiny graphene pores

The surface of a single cell contains hundreds of tiny pores, or ion channels, each of which is a portal for specific ions. Ion channels are typically about 1 nanometer wide; by maintaining the right balance of ions, they keep cells healthy and stable.

Now researchers at MIT have created tiny pores in single sheets of graphene that have an array of preferences and characteristics similar to those of ion channels in living cells.

Each graphene pore is less than 2 nanometers wide, making them among the smallest pores through which scientists have ever studied ion flow. Each is also uniquely selective, preferring to transport certain ions over others through the graphene layer.

MIT Sloan
Management Review

October 5, 2015

‘People Analytics’ Through Super-Charged ID Badges

What if “people analytics“ were able to bring new clarity to the hidden patterns of why some people are more successful at their jobs than others? What if managers could essentially read people the way they read statistics?

Those are two of the questions that drive Ben Waber, the CEO and a cofounder of Humanyze. Using a sort of turbo-charged company ID badge to track all sorts of data points about employees, Humanyze helps companies find surprising connections and insights in data about what its most effective employees do differently. The company is a spinoff of the MIT Media Lab, founded by a group that includes MIT professor Alexander “Sandy“ Pentland.